circuit note cn - 0248 circuits from the lab? reference circuits are engineered and tested for quick and easy system integration to help solve todays analog, mixed - signal, and rf design challenges. for more i nformation and/or support , visit www.analog.com/cn0248 . devices connected /referenced ADRF6510 30 mhz dual programmable filters and variable gain amplifiers adl5387 50 mhz to 2 ghz quadrature demodulator adl5336 lf to 1 ghz vga with 48 db gain control range and programmable rms detectors an iq demodulator - based if - to - baseband receiver with if and baseband variable gain and programmable base band filtering rev. 0 circuits from the lab? circuits from analog devices have been designed and built by analog devices engineers. standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. however, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. accordingly, in no event shall analog devices be liable f or direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any circuits from the lab circuits. (continued on last page) one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s. a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. evaluation and desig n support circuit evaluation boards ADRF6510 evaluation board (ADRF6510 - evalz) adl5387 evaluation board (adl5387 - evalz) adl5336 evaluation board (adl5336 - evalz) ad8130 evaluation board (ad8130 - ebz) two required design and integration files schematics, layout files, bill of materials circuit function and benefits this circuit is a flexible, frequency agile if - to - baseband receiver . variable gain at both if and baseband is used to adjust the signal level. the ADRF6510 baseband adc driver also includes a programmable low - pass filter that eliminates out - of - channel blockers and noise . the bandwidth of this filter can be dynamically adjusted as the bandwidth of the input signal cha nges. this ensures that the available dynamic range of the adc that this circuit drive s is fully used . the core of the circuit is an iq d emodulator. the 2 lo based phase - splitting architecture of the adl5387 a llows for operation over a wide frequency range. precise quadrature balance and low output dc offsets ensure that there is minimal degradation of the error vector magnitude ( evm ). the interface s between all of the components in this circuit are fully diff erential . where dc coupling is required between stages, the bias levels of the adjacent stages are compatible with each other. ADRF6510 i q rf div by 2 adl5387 2xlo 0 90 adf4350 adl5336 ad9248 bits bits 10285-001 vco core f igure 1. direct conversion receiver simplified schematic (all connections and decoupling not shown )
cn-0248 circuit note rev. 0 | page 2 of 6 circuit description receiver architecture a direct c onversion (a lso known as a homodyne or zero if) architecture for a receiver is presented in this circuit note . direct co nversion radios perform just one frequency translation compared to a superheter odyne receiver that can perform several frequency translations. one frequency translation is advantageous because it ? reduces receiver complexity and the number of stages needed ; increas ing performance and reduc ing power consumption ? avoids image rejection issues and unwanted mixing products; one lpf at baseband is all that is needed ? has high selectivity ( adjacent - channel rejection ratio [ acrr ]) figure 1 shows the basic simplified schematic of the system that consist s of cascaded if variable gain amplifiers ( vga s) with integrated automatic gain control ( agc ) loops , followed by a quadrature demodulator and by programmable low - pass filters with variable baseband gain . the grayed out components shown in figure 1 ( adf4350 and ad9248 ) are included for clarity but were not included during system - level measurements (see the common va r iati ons section for more information on these devices) . ideally, the input of the first stage and the output of the last stage should set the dynamic range (signal - to - noise ratio) of the system. practically, this may not b e the case . having a cascaded vga before the quadrature demodulator not only add s more gain to the system , but it also help s with overall system noise performance if the noise figure of the vga is less than that of the quadrature demodulator , and if the vg a still has gain , and it is not attenuating . the noise figures of the subsequent stages are divided by the gain of the initial vga . another benefit of having a vga ( vs. just having a fixed gain amplifier) is that an agc loop can be designed to level the in coming signal to the quadrature demodulator . it is important to have this ability to limit the signal levels applied to the quadrature demodulator and any subsequent stages . if vgas and agc loops the if vga and agc loop functions are accomplished with the adl5336 . it has two cascadable vgas, each with 24 db of analog dynamic range and the ability to digitally change the maximum gain on each vga via a spi port . to achieve the signal leveling agc function, e ach adl5336 vga has a square law detector connected to its output through a programmable attenuator . the detector compares the output of the attenuator to an internal reference of 63 mv rms . if there is a differe nce between the output of the attenuator and the 63 mv rms reference, an error current is produced and is integrated onto a c agc capacitor . the agc loop is closed by connecting the dto1/ dto 2 pin to the gain1/ gain 2 pin . f or the agc loop to function properly , p ull t he mode pin low , caus ing a negative vga gain slope . each adl5336 vga has a n allowable range of input power over which the agc will level to a particular setpoint . outside that range, the vga output ei ther increase s or decrease s db -f or - db with the input (assuming the vga i s not in compression or that the signal is no t in the noise floor ). iq demo dulator from the adl5336 , the signal is routed to the adl5387 , w here it is demodulated and the frequency is translated to a zero if . the adf4350 synthesizer can provide the required 2 lo signal to the adl5387 (see the common variations section); however, a signal generator was used instead of the adf4350 for actual testi ng . the adl5387 uses two double - balanced mixers, one for the i channel and one for the q channel . the lo provided to the mixers is generated using a divide - by - two quadrature phase splitter. this provides the 0 and 90 signals fo r the i and q channels . there is about 4.5 db of conversion gain provided by the adl5387 from the rf input to the baseband i and q outputs . low -p ass filter, baseband vga , and adc driver the low - pass filtering , baseband gain , and adc driver functions are all achieved using the ADRF6510 . the signal , now in its separate i and q paths , i s applied to the ADRF6510 where t he signal is first amplified by the preamplifier , then low -pass filtered to suppress any unwanted out - of - band signals and/or noise, and finally amplified by the vga . each channel of the ADRF6510 can be broken up into three stages: ? preamplifier ? programmable low -pass filter ? vga and output driver the preamplifier has a user - selectable gain, via the gnsw pin, of either 6 db or 12 db . the low -pass filter can be programmed for a corner frequency of 1 mhz to 30 mhz in 1 mhz steps via the spi port . the vga has a 50 db gain range with a gain slope of 30 mv/db . the gain of the vga is controlled via the gain pin , and it can range from ?5 db to +45 db when th e gnsw pin is pulled low to +1 db to +51 db when the gnsw pin is pulled high . the output driver has the ability to drive 1.5 v p- p differential into a 1 k? load while maintaining a hd2 and a hd3 of better than 60 dbc . the maximum cw signal that can be applied to the low - pass filters, while still maintaining acceptable hd levels in the ADRF6510 , is 2 v p-p . in applications where a large out - of - band interferer is present that could overload the input of either the adl5387 and/o r the ADRF6510 , the out - of - band interferer (and the in - band desired signal) can be attenuated by the adl5336 vga . once the out of - band interferer is rejected by the low - pass filter of the ADRF6510 , the wanted signal can then be amplified with the x - amp vgas that follow the filters of the ADRF6510 . from the ADRF6510 , the i q sig nal can be applied to an appropriate analog - to - digital converter (adc), such as the ad9248 .
circuit note cn- 0248 rev. 0 | page 3 of 6 measurement results a 4 - qam, 5 msps modulated signal was applied to the input of the adl5336 . for more information on the test setup, see the circuit evaluation and test section. evm is a measure of the quality of the performance of a digital transmitter or receiver and is a measure of the deviation of the actual constellation points from their ideal locations, due to both magnitude and phase errors. this is shown in figure 2 . 10285-002 q i error vector measured signal phase error (i/q error phase) magnitude error (i/q error phase) ideal signal (reference) 0 figure 2. evm plot figure 3 show s the system evm vs . the input power to the adl5336 while the max imum gains on the vgas ar e set to 15.2 db and 19.5 db for vga1 and vga2 , respectively . several agc setpoint combinations were tested . figure 4 is also system evm v s. the input power to the adl5336 ; however, the gain of the vgas was set 9.7 db and 13.4 db, respectively . the same agc setpoint combinations were tested. 0 ?50 ?95 35 evm (db) pin (dbm) 10285-003 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 ?85 ?75 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 15 25 vga1 = 88mv rms, vga2 = 88mv rms vga1 = 88mv rms, vga2 = 707mv rms vga1 = 250mv rms, vga2 = 250mv rms vga1 = 707mv rms, vga2 = 88mv rms vga1 = 707mv rms, vga2 = 707mv rms vga1 = 88mv rms, vga2 = 250mv rms vga1 = 250mv rms, vga2 = 88mv rms vga1 = 250mv rms, vga2 = 707mv rms vga1 = 707mv rms, vga2 = 250mv rms figure 3 . system evm, digital vga gains = 11 0 ?50 ?95 35 evm (db) pin (dbm) 10285-004 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 ?85 ?75 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 15 25 vga1 = 88mv rms, vga2 = 88mv rms vga1 = 88mv rms, vga2 = 707mv rms vga1 = 250mv rms, vga2 = 250mv rms vga1 = 707mv rms, vga2 = 88mv rms vga1 = 707mv rms, vga2 = 707mv rms vga1 = 88mv rms, vga2 = 250mv rms vga1 = 250mv rms, vga2 = 88mv rms vga1 = 250mv rms, vga2 = 707mv rms vga1 = 707mv rms, vga2 = 250mv rms figure 4 . system evm, digital vga gains = 00 figure 3 and figure 4 illustrate the i mportance of keeping the sig nal levels applied to the ADRF6510 low enough not to compress the input stage and/or filter . at the highest of agc setpoints (500 mv rms and 707 mv rms), the input of the adl5387 iq demodulator is starting to compress and add s additional degradation to the evm . the best evm is achieved when the agc setpoints are at their lowest (8 8 mv rms) . evm is already beginning to degrade when the setpoints are 250 mv rms . figure 5 compares the evm between the minimum and the maximum digital gain settings (both vgas were set to either a gain code of 11 or a gain code of 00) on the adl5336 vgas when vga1 a nd vga2 setpoints are 250 mv rms and 88 mv rms, respectively . 0 ?50 ?95 35 evm (db) pin (dbm) 10285-005 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 ?85 ?75 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 15 25 gain = 11 gain = 00 figure 5 . system evm with vga1 setpoint = 250 mv rms and vga2 setpoint = 88 mv rms for the given agc setpoints , when the maximum gain code was 11, the handoff from vga2 to vga1 occurs after vga2 runs out of the gain range ; th erefore, the signal level being applied to the ADRF6510 continues to increase (and degrade evm) until vga1 reaches its setpoint . once vga1 reaches its own setpoint , the evm levels off again ; th erefore, the signal level being applied to the ADRF6510 does not chang e until vga1 runs out of the gain range at about 5 dbm of input power . when the maximum gain code was set to 00, both vgas have more attenuation available, thus allowing vga2 to shift its dynamic range such that it does not
cn- 0248 circuit note rev. 0 | page 4 of 6 reach its setpoint at as low an input power as when the maximum gain code was 11 . this allows vga2 to keep its setpoint at h igher input powers, thus allowing the handoff from vga2 to vga1 to take place before vga2 runs out of gain . this ensures that the signal level applied to the ADRF6510 is maintained at a constant level until t he uppermost of the input power range. figure 6 compares the evm between the minimum and the maximum digital gain settings (both vgas were set to either a gain code of 11 or a gain code of 00) on the adl5336 vgas ; however, the vga1 and vga2 setpoints were 707 mv rms and 88 mv rms, respectively. 0 ?50 ?95 35 evm (db) pin (dbm) 10285-006 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 ?85 ?75 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 15 25 gain = 11 gain = 00 figure 6 . system evm with vga1 setpoint = 707 mv rms and vga2 setpoint = 88 mv rms the same dynamics are occurrin g in figure 6 as they were in figure 5 , only they are much more exaggerated . w hen the max imum gain code is 00 , vga2 reaches its setpoint at around ? 40 dbm input power . it maintains its setpoint until about ? 10 dbm, at which point, vga1 has not reached its setpoint of 707 mv rms . vga1 does not reach its setpoint until about 0 dbm , and the evm starts to level off somewhat . when the maximum gain is set to 11, this same behavior happens again ; however, vga2 maintains its setpoint only to about ?20 dbm because there is more gain available to attain the prescribed setpoints. c ommon variations system and synthesier the signal generator that provides the 2 lo for the adl5387 can be replaced by a wideband synthesizer , such as the adf4350 , which has an integrated vco . the adf4350 belongs to a family of synthesizers that operate over a wide frequency range , from 135 mhz to 4350 mhz, and that has varying phase noise and output power metrics, making it easy to find the device to match the required specifications of the appli cation . system and adc adding an adc to the system to sample the i and q signals of the ADRF6510 is a natural progression to complete the analog signal chain . a dual adc , such as the ad9248 , provides 14 bits of resolution and is offered in 20 msps , 40 msps, or 65 msps sampling rates . an antialiasing filter is recommended between the output of the ADRF6510 and the ad9248 . r efer to the ADRF6510 data sheet for the antialiasing filter design example. ADRF6510 output c ommon - mode vol tage considerations the ADRF6510 output common - mode voltage is adjustable from 1.5 v to 3.0 v without loss of drive capability . many modern adcs have input common - mode voltages of less than 1.5 v . driving the vocm pin to an output common - mode voltage less than 1.5 v start s to degrade the distortion performance of the ADRF6510 ; however, it is still functional for less than 1.5 v common - mode voltage levels . to main tain distortion performance , a dc level shifting circuit may be required, or an integrated filter and vga device with a lower common - mode voltage , such as the adrf6516 , can be used. circuit evaluation and t e st equipment needed /used signal g enerators include the following: ? agilent e4438c vector signal generator ? agilent e4438c signal generator the b aseband signal capture device is the ? agilent dso90604a o scilloscope the evm computation device (s) include the fol lowing: ? agilent 89600 vsa software ? pc running windows xp connected to o scilloscope via a usb cable the po wer s upply includes the following: ? 5 v s upply. all boards require +5 v with the exception of the ad8130 boards that require 5 v the e valuation b oards include the following: ? adl53 3 6 - e va l z (one required) ? adl5387 - e va l z (one required) ? ADRF6510 - e va l z (one required) ? ad8130 - ebz (two required)
circuit note cn-0248 rev. 0 | page 5 of 6 getting started to use the adl5336 and ADRF6510 , the evaluation software is needed to control various aspects of each part . this software can be found on the respective product web pages under the to ols, software, & simulations models link. once the software is download ed and installed, plug in the usb cables from the computer to the evaluation boards and then run the software for the part that needs to be control led . functional block diagram figure 7 shows the functional block diagram of the t est setup that was used for testing the receive chain. the adl5336 evaluation board onl y allows for single - ended input and output. the same is true for the rf input on the adl5387 board. the rf output port on the vector signal generator is only single ended; therefore, a balun between the generator and the input of the adl5336 is necessary. as shown in figure 7 , the rest of the signal path is differential until the ad8130 difference amplifiers. the differential - to - signal - ended conversion was needed because the oscilloscope only allows for sampling of single - ended signals while being controlled by the vsa software. setup and test the first step of the setup of the receiver test is to turn on all test equipment. while the test equipment is warming up, the boards must be configured correctly for prope r use in this signal chain. on the adl5336 , ensure that the 0 ? jumper resistors that connect the vga1 output to the vga2 input are populated on the adl5387 boa rd, bypass the output baluns for full differential , dc - coupled signal paths between the adl5387 and the ADRF6510 . on the ADRF6510 board, do the following: ? bypass t he input and output baluns ? place 1 k? differential output loads on the output signal lines (two 500 ? resistors to ground will suffice on each output path) ? replace the stock c ofs capacitors with 1 f capacitors collect the evaluation boards and connect all the signal paths together , as shown in figure 7 . connect all boards to +5 v and the two ad8130 boards to ?5 v as well. ensure that the power supply current is consistent with what is expected. as shown in figure 7 , make the following connections: ? connect the single - ended, 50 ? output of the vector signal generator to input1 of the adl5336 evaluation board. ? connect the i signal path output of the ad8130 to i nput 1 on the oscilloscope , and connect the q signal path output of the ad8130 to i nput 3 of the oscilloscope. ? connect the usb cable from the pc t o the oscilloscope. ? connect the rf port of the signal generator to the lo input of the adl5387 evaluation board. on the agilent e4438c signal generator, do the following: ? set the frequency to 400 mhz ? set th e amplitude to 0 dbm ? turn the rf port on on the agilent e4438c vector signal generator , do the following: ? set the rf carrier frequency to 200 mhz ? set the amplitude to ?30 dbm ? turn the rf port on ? turn on the custom arb inside the vector signal generato r ? s et the signal to 4 - qam, symbol rate to 5 msps, and pulse shaping filter alpha to 0.35 on the pc , start the agilent 89600 vsa software. in the vsa software , do the following: ? t urn the digital demodulator on ? set the input to the i+ jq option ? set the f requency to 0 hz, symbol rate to 5 msps, and alpha to 0.35 ADRF6510 i q adl5387 2xlo adl5336 agilent dso 90604 oscilloscope agilent e4438c signal generator usb adl5336 evaluation board adl5387 evaluation board ADRF6510 evalution board ad8130 evalution boards adl5387-evalz ADRF6510-evalz ad8130-ebz ad8130-ebz +5v to all boards ?5v to ad8130 boards gnd to all boards power supplies adl5336-evalz 10285-007 div by 2 0 90 agilent e4438c vector signal generator computer agilent 89600 vsa software figure 7 . functional block diagram for testing direct conversion receiver
cn- 0248 circuit note rev. 0 | page 6 of 6 the signal metrics on the vector signal generator must match the metrics on the vsa softw are. when the software starts up, it should display the iq c onstellation pane and the spectrum pane. add the informatio n window on the vsa software by taking the following steps: 1 . click display 2 . c lick layout 3 . select grid 2 2 by default, the other two panes t hat have appeared should be an error vector vs . time and the information window , syms/errs . if this is not the case , do the following: 1 . double - click the title of any pane 2 . select syms/errs in the window that appears the syms/errs pane present s a number of r esults, including evm. the software should be locked onto the signal and reporting an evm number. the agc setpoint, maximum gain, and filter bandwidth can all be set with the respective control software of the individual devices . power control at the input of the adl5336 can be done via a power sweep on the vector signal analyzer. a ?80 dbm to almost +16 dbm sweep was performed to test the receiver in this test setup. the gain on the ADRF6510 was always set to achieve a 1.5 v p - p differential output level, assuming there was sufficient gain to achieve this. in some cases , for very small signal levels, the ADRF6510 did not have enough gain to reach the 1.5 v p - p differential level. learn mo re cn - 0248 design support package: http://www.analog.com/cn0248 - designsupport ardizzoni, john. a practical guide to high - speed printed - circuit - board layout , analog dialogue 39 - 09, september 2005. mt - 031 tutorial, grounding data converters and solving the mystery of "agnd" and "dgnd." analog device s. mt - 073 tutorial, high speed variable gain amplifiers (vgas) . analog devices. mt - 101 tutorial, decoupling techniques , analog devices. adisimpll design tool adisimrf design tool an - 0996 application note. the advantages of using a quadrature digital upconverter (qduc) in point - to - point microwave transmit systems. analog devices. an - 1039 application note. correcting imperfections in iq modulators to improve rf signal fidelity . analog devic es. cn - 0134 circuit note, broadband low error vector magnitude (evm) direct conversion transmitter , analog devices data sheets and evaluation boards ADRF6510 data sheet and evaluation board adl5387 data sheet and evaluation board adl5336 data sheet and evaluation board adf4350 data sheet and evaluation board ad9248 data sheet and evaluation board adrf6516 data sheet and evaluation board ad8 130 data sheet and evaluation board revision history 4 / 12 rev ision 0 : initial version (continued from first page) circuits from the lab circuits are intended only for use with analog devices products and are the intellectual property of an alog devices or its licensors. while you may use the circuits from the lab circuits in the design of your product, no other license is granted by implication or other wise under any patents or other intellectual property by application or use of the circuits from the l ab circuits. information furnished by analog devices is believed to be accurate and reliable. however, circuits from the lab circuits are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by analog devices for their use, nor for any infringements of patents or other right s of third parties that may result from their use . analog devices reserves the right to change any circuits from the lab circuits at any time without notice but is under no obligation to do s o. ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. cn10285 - 0 - 4/12(0)
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